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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd77115, 77115a 16-bit fixed-point digital signal processor document no. u14867ej5v0ds00 (5th edition) date published august 2004 ns cp(k) printed in japan data sheet 2000, 2004 the mark shows major revised points. description the pd77115 and pd77115a are 16-bit fixed-point digital signal processors (dsp). the pd77115 and pd77115a are ram based dsp and have the spec ific circuit for audio application. unless otherwise specified, the pd77115 refers to pd77115 and 77115a. for details of the functions of the pd77115, refer to the following user?s manuals: pd77111 family user?s manual - architecture : u14623e pd77016 family user?s manual - instructions : u13116e features ? instruction cycle (operating clo ck) 13.3 ns min. (75 mhz max.) ? memory internal instruction ram 11.5k words 32 bits internal data ram 16k words 16 bits 2 banks ? peripherals audio serial interface secure digital (sd) card interface 16-bit timer 16-bit host interface 8-bit port ? supply voltage dsp core voltage 2.0 to 2.7 v (max. operation speed 50 mhz) 2.3 to 2.7 v (max. operation speed 75 mhz) i/o pin voltage 2.7 to 3.6 v ? power consumption typ. 50 mw (2.0 v, 50 mhz operation) ordering information part number package pd77115f1-cn6 80-pin plastic fbga (9 9) pd77115gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) pd77115af1-xxx-cn6 80-pin plastic fbga (9 9) remark xxx indicates rom code suffix.
data sheet u14867ej5v0ds 2 pd77115, 77115a block diagram audio serial interface peripheral units data memory unit operation unit program control unit sd card interface port host interface x memory data addressing unit x memory y memory data addressing unit y memory interrupt control loop control stack pc stack pll mac 16 x 16 + 40 -> 40 alu(40) r0 to r7 x bus y bus int1 to int4 reset clkout clkin wakeup pll0 to pll3 note main bus instruction memory debug interface cpu control note the pll0 to pll3 pins are multiplexed with the p4 to p7 pins. bsft timer dma bus
data sheet u14867ej5v0ds 3 pd77115, 77115a function pin groups reset int1 to int4 hcs ha0,ha1 hrd hre hwr hwe hd0 to hd15 + 3 v + 2.5 v iv dd ev dd reset, interrupt system control clock audio serial interface host interface port debug interface (8) (4) (2) (4) (2) (16) so soen/lrclk sck/bclk si sien/mclk clkin clkout wakeup tdo,tice tck,tdi,tms,trst p0 to p3,p4/pll0 to p7/pll3 gnd sd card interface sddat sdcr sdclk remark the p4 to p7 pins are multiplexed with pll0 to pll3 pins.
data sheet u14867ej5v0ds 4 pd77115, 77115a pd77213 15.5 k 32 64k 32 18 k 16 each 32 k 16 each 1 m 16 (8 k 16, using sd i/f) 8.33 ns (120 mhz) sd card i/f pd77210 31.5 k 32 30 k 16 each 1 m 16 6.25 ns (160 mhz) integer multiple of 10 to 64 (external pin) 2 channels (time-division, audio) 16 bits (some are alternative with host) 2 channels (16-bit resolution) ? dsp core: 1.5 v i/o pins: 3 v 161-pin fbga 144-pin lqfp pd77115,77115a 11.5 k 32 none 16 k 16 each none none integer multiple of 1 to 16 (external pin) 1 channel (audio codec) 16-bit bus 8 bits 1 channel (16-bit resolution) sd card i/f 80-pin tqfp 80-pin fbga pd77114 8 k 16 each ? 100-pin tqfp pd77113a 3.5 k 32 48 k 32 16 k 16 each 32 k 16 each none ? 80-pin fbga pd77112 16 k 16 each ? 100-pin tqfp pd77111 1 k 32 31.75 k 32 3 k 16 each 16 k 16 each none 13.3 ns (75 mhz) integer multiple of 1 to 16 (mask option) ? 80-pin tqfp 80-pin fbga pd77110 35.5 k 32 none 24 k 16 each none none 32 k 16 each 15.3 ns (65 mhz) integer multiple of 1 to 8 (external pin) 2 channels (speech codec) 8-bit bus 4 bits none ? dsp core: 2.5 v i/o pins: 3 v 100-pin tqfp int. instruction ram int. instruction rom data ram (x/y memory) data rom (x/y memory) ext. instruction ext. data memory (x/y memory) serial interface host interface general-purpose port (i/o programmable) timer others dsp function list item memory space (words bits) instruction cycle (at maximum operating speed) multiple peripheral supply voltage package
data sheet u14867ej5v0ds 5 pd77115, 77115a pin configurations 80-pin plastic fine pitch bga (9 9) pd77115f1-cn6 pd77115af1-xxx-cn6 (bottom view) (top view) jhgfedcba abcdefghj 9 8 7 6 5 4 3 2 1 index mark pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 ev dd c3 sddat e6 gnd g8 hre a2 nc c4 gnd e7 hwr g9 ev dd a3 ev dd c5 int3 e8 ev dd h1 gnd a4 iv dd c6 trst e9 clkout h2 ev dd a5 int2 c7 tice f1 ev dd h3 hd12 a6 reset c8 tdo f2 p0 h4 ev dd a7 tdi c9 ha0 f3 p3 h5 gnd a8 i.c. d1 soen/lrclk f4 hd9 h6 hd2 a9 i.c. d2 p5/pll1 f5 hd4 h7 iv dd b1 nc d3 so f6 hrd h8 hd0 b2 si d4 p7/pll3 f7 hwe h9 gnd b3 sdcr d5 sdclk f8 clkin j1 nc b4 gnd d6 int4 f9 hcs j2 gnd b5 wakeup d7 iv dd g1 p1 j3 hd13 b6 int1 d8 ha1 g2 hd15 j4 hd10 b7 tms d9 gnd g3 hd14 j5 hd7 b8 tck e1 p6/pll2 g4 hd11 j6 hd6 b9 i.c. e2 p4/pll0 g5 hd8 j7 hd3 c1 sien/mclk e3 gnd g6 hd5 j8 gnd c2 sck/bclk e4 p2 g7 hd1 j9 i.c.
data sheet u14867ej5v0ds 6 pd77115, 77115a 80-pin plastic tqfp (fine pitch) (12 12) (top view) pd77115gk-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 si nc sien/mclk sck/bclk so soen/lrclk p7/pll3 gnd p6/pll2 p5/pll1 p4/pll0 ev dd p3 p2 p1 p0 hd15 gnd nc hd14 tice i.c. i.c. tdo ha1 ha0 gnd iv dd gnd ev dd clkin clkout hwr hrd hcs hwe hre ev dd gnd hd0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ev dd gnd hd13 hd12 hd11 hd10 hd9 hd8 hd7 ev dd gnd hd6 hd5 hd4 hd3 hd2 iv dd gnd i.c. hd1 ev dd sddat nc sdcr gnd ev dd sdclk gnd iv dd wakeup int1 int2 int3 int4 reset trst tms tdi i.c. tck
data sheet u14867ej5v0ds 7 pd77115, 77115a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 si 21 ev dd 41 hd0 61 tck 2 nc 22 gnd 42 gnd 62 i.c. 3 sien/mclk 23 hd13 43 ev dd 63 tdi 4 sck/bclk 24 hd12 44 hre 64 tms 5 so 25 hd11 45 hwe 65 trst 6 soen/lrclk 26 hd10 46 hcs 66 reset 7 p7/pll3 27 hd9 47 hrd 67 int4 8 gnd 28 hd8 48 hwr 68 int3 9 p6/pll2 29 hd7 49 clkout 69 int2 10 p5/pll1 30 ev dd 50 clkin 70 int1 11 p4/pll0 31 gnd 51 ev dd 71 wakeup 12 ev dd 32 hd6 52 gnd 72 iv dd 13 p3 33 hd5 53 iv dd 73 gnd 14 p2 34 hd4 54 gnd 74 sdclk 15 p1 35 hd3 55 ha0 75 ev dd 16 p0 36 hd2 56 ha1 76 gnd 17 hd15 37 iv dd 57 tdo 77 sdcr 18 gnd 38 gnd 58 i.c. 78 nc 19 nc 39 i.c. 59 i.c. 79 sddat 20 hd14 40 hd1 60 tice 80 ev dd
data sheet u14867ej5v0ds 8 pd77115, 77115a pin name clkin : clock input clkout : clock output ev dd : power supply for i/o pins gnd : ground ha0, ha1 : host data access hcs : host chip select hd0 to hd15 : host data bus hrd : host read hre : host read enable hwe : host write enable hwr : host write i.c. : internally connected int1 to int4 : interrupt iv dd : power supply for dsp core nc : non-connection p0 to p3 : port p4/pll0 to p7/pll3 : port/ pll setting input reset : reset sck/bclk : serial clock input/ output sdclk : sd card clock output sdcr : sd card command output/ response input sddat : sd card data input/ output si : serial data input sien/mclk : serial input enable/ master clock input so : serial data output soen/lrclk : serial output enabl e/ left right clock input/ output tck : test clock input tdi : test data input tdo : test data output tice : test in-circuit emulator tms : test mode select trst : test reset wakeup : wakeup from stop mode
data sheet u14867ej5v0ds 9 pd77115, 77115a contents 1. pin function............................................................................................................... .................. 10 1.1 pin function description ................................................................................................... ...... 10 1.2 connection of unused pins .................................................................................................. ... 14 2. function outline........................................................................................................... ............ 15 2.1 program control unit ....................................................................................................... ........ 15 2.2 arithmetic unit ............................................................................................................ .............. 16 2.3 data memory unit ........................................................................................................... .......... 17 2.4 peripheral unit ............................................................................................................ .............. 17 3. reset function............................................................................................................. .............. 18 3.1 hardware reset............................................................................................................. ............ 18 3.2 initializing pll........................................................................................................... ................ 18 4. functions of boot-up rom .................................... ............................................................. . 18 4.1 boot at reset.............................................................................................................. ............... 18 4.2 reboot..................................................................................................................... ................... 19 4.3 signature operation ........................................................................................................ ......... 19 5. standby modes .............................................................................................................. ............. 20 5.1 halt mode .................................................................................................................. .............. 20 5.2 stop mode .................................................................................................................. .............. 20 6. memory map ................................................................................................................. ................ 21 6.1 instruction memory......................................................................................................... .......... 21 6.2 data memory ................................................................................................................ ............. 23 7. instructions ................................................................................................................ ................ 25 7.1 outline of instructions .................................................................................................... .......... 25 7.2 instruction set and operation . ............................................................................................. ... 26 8. electrical specifications .................................................................................................. .. 32 9. packages ... ................................................................................................................. ................... 51 10. recommended soldering conditions ................................................................................ 53
data sheet u14867ej5v0ds 10 pd77115, 77115a 1. pin function because the pin numbers differ depending on the package, re fer to the diagram of the package to be used. 1.1 pin function description ? power supply pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: iv dd a4,d7,h7 37,53,72 ? power to dsp core (+2.5 v) ? ev dd a1,a3,e8,f1, g9,h2,h4 12,21,30,43,51, 75,80 ? power to i/o pins (+3 v) ? gnd b4,c4,d9,e3, e6,h1,h5,h9, j2,j8 8,18,22,31, 38,42,52,54, 73,76 ? ground ? system control pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: clkin f8 50 input system clock input ? clkout e9 49 output internal system clock output ? pll0 to pll3 e2,d2,e1,d4 11,10,9,7 input pll multiple rate setting pin pll3 to pll0: 0000 : x16, 0001 : x1, 0010 : x2, 0011 : x3, 0100 : x4, 0101 : x5, 0110 : x6, 0111 : x7, 1000 : x8, 1001 : x9, 1010 : x10, 1011 : x11, 1100 : x12, 1101 : x13, 1110 : x14, 1111 : x15 p4 to p7 reset a6 66 input internal system reset signal input ? wakeup b5 71 input stop mode release signal input. ? when this pin is asserted active, the stop mode is released. ? interrupt pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: int1 to int4 b6,a5,c5,d6 70,69,68,67 input external maskable interrupt input. detected at the falling edge. ?
data sheet u14867ej5v0ds 11 pd77115, 77115a serial interface pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: sck/bclk c2 4 i/o serial clock input/output sck : standard serial interface(input) bclk : audio serial interface(i/o) ? soen/lrclk d1 6 i/o serial output enable / left right clock input/output soen : standard serial interface(input) lrclk : audio serial interface(i/o) ? so d3 5 output (3s) serial data output ? sien/mclk c1 3 input serial i nput enable / master clock input sien : standard serial interface mclk : audio serial inte rface (master clock input when master mode) ? si b2 1 input serial data input ? remark the pins marked ?3s? under the heading ?i/o? go into a high-impedance stat e on completion of data transfer and input of the hardware reset (reset) signal. sd card interface pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: sdclk d5 74 output sd card clock output ? sdcr b3 77 i/o (3s) sd card command/response input : response output : command ? leave pulled up. ? sddat c3 79 i/o (3s) sd card data input/output input : read data output : write data ? leave pulled up. ? remark the pins marked ?3s? under the heading ?i/o? go into a high-impedance state when the sd card interface is not being accessed.
data sheet u14867ej5v0ds 12 pd77115, 77115a host interface pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: ha1 d8 56 input specifies the register to be accessed by hd15 to hd0. 1: accesses the host interface status register (hst). 0: accesses the host transmit data register (hdt (out)) when read (hrd = 0), and host receive data register (hdt (in)) when written (hwr = 0). ? ha0 c9 55 input specifies the register to be accessed by hd15 to hd0. 1: accesses bits 15 to 8 of hst, hdt (in), and hdt (out). 0: accesses bits 7 to 0 of hst, hdt (in), and hdt (out). when 8-bit mode, this signal becomes valid. when 16-bit mode, this signal becomes invalid. ? hcs f9 46 input chip select input ? hrd f6 47 input host read input ? hwr e7 48 input host write input ? hre g8 44 output host read enable output ? hwe f7 45 output host write enable output ? hd0 to hd15 h8,g7,h6,j7, f5,g6,j6,j5, g5,f4,j4,g4, h3,j3,g3,g2 41,40,36,35, 34,33,32,29, 28,27,26,25, 24,23,20,17 i/o (3s) 16-bit host data bus ? remark the pins marked ?3s? under the heading ?i/o? go into a high-impedance state when the host interface is not being accessed. i/o ports pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: p0 f2 16 i/o ? p1 g1 15 i/o ? p2 e4 14 i/o ? p3 f3 13 i/o ? p4 e2 11 i/o pll0 p5 d2 10 i/o pll1 p6 e1 9 i/o pll2 p7 d4 7 i/o general-purpose i/o port pll3
data sheet u14867ej5v0ds 13 pd77115, 77115a debugging interface pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: tdo c8 57 output ? tice c7 60 output ? tck b8 61 input ? tdi a7 63 input ? tms b7 64 input ? trst c6 65 input for debugging ? others pin no. pin name 80-pin fbga 80-pin tqfp i/o function shared by: i.c. a8,a9,b9,j9 39,58,59,62 ? internally connected. leave this pin unconnected. ? nc a2,b1,j1 2,19,78 ? no-connect pins. leave these pins unconnected. ? caution if any signal is input to these pins or if an attempt is made to read these pins, the normal operation of the pd77115 is not guaranteed.
data sheet u14867ej5v0ds 14 pd77115, 77115a 1.2 connection of unused pins 1.2.1 connection of function pins when mounting, connect unused pins as follows: pin i/o recommended connection int1 to int4 input connect to ev dd . sck/bclk i/o si input connect to ev dd or gnd. sien/mclk input connect to gnd. soen/lrclk i/o so output leave unconnected sdclk output sdcr i/o sddat i/o connect to ev dd via pull-up resistor, or connect to gnd via pull-down resistor. ha0, ha1 input connect to ev dd or gnd. hcs, hrd, hwr input connect to ev dd . hre, hwe output leave unconnected. hd0 to hd15 note i/o p0 to p3 i/o connect to ev dd via pull-up resistor, or connect to gnd via pull-down resistor. tck input connect to gnd via pull-down resistor. tdo, tice output leave unconnected. tms, tdi input leave unconnect ed. (internally pulled up). trst input leave unconnected. (internally pulled down). clkout output leave unconnected. wakeup input connect to ev dd . note these pins may be left unconnected if hcs, hrd, and hwr are fixed to the high level. however, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 1.2.2 connection of no-function pins pin i/o recommended connection i.c. ? leave unconnected. nc ? leave unconnected.
data sheet u14867ej5v0ds 15 pd77115, 77115a 2. function outline 2.1 program control unit this unit is used to execute instruct ions, and control branching, loops, inte rrupts, the clock, and the standby mode of the dsp. 2.1.1 cpu control a three-stage pipeline architecture is em ployed and almost all the instructions, except some instructions such as branch instructions, are ex ecuted in one system clock. 2.1.2 interrupt control interrupt requests input from external pins (int1 to int4) or generated by the internal peripherals (serial interface and host interface) are serviced. the in terrupt of each interrupt source can be enabled or disabled. multiple interrupts are also supported. 2.1.3 loop control task a loop function without any hardware over head is provided. a loop stack with f our levels is provided to support multiple loops. 2.1.4 pc stack a 15-level pc stack that stores the program counter supports multip le interrupts and subroutine calls. 2.1.5 pll a pll is provided as a clock generator t hat can multiply an external clock i nput to supply an operating clock to the dsp. a multiple of 1 to 16 can be set by pins(pll0 to pll3). two standby modes are available for lowering the pow er consumption while the dsp is not in use. halt mode : set by execution of t he halt instruction. t he current consumption drops to several ma. the normal operation mode is recovered by an interrupt or hardware reset. stop mode : set by execution of the stop instruction. the current consumption drops to several 10 a. the normal operation mode is recovered by hardware reset or wakeup pin. 2.1.6 instruction memory 64 words of the instruction ram are allocated to interrupt vectors. a boot-up rom that boots up t he instruction ram is provided, and the instruction ram can be initialized or rewritten by host boot (boot via host interface). the pd77115 has 11.5k-word instruction ram.
data sheet u14867ej5v0ds 16 pd77115, 77115a 2.2 arithmetic unit this unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data alu, 40-bit barrel shifter, and eight 40-bit general- purpose registers. 2.2.1 general-purpose registers (r0 to r7) these eight 40-bit registers are used to input/output data for ar ithmetic operations, and l oad or store data from/to data memory. a general-purpose register (r0 to r7) is made up of three parts: r0l to r7l (bits 15 to 0), r0h to r7h (bits 31 to 16), and r0e to r7e (bits 39 to 32). depending on the ty pe of operation, rnl, rn h, and rne are used as one register or in different combinations. 2.2.2 multiply accumulator (mac) the mac multiplies two 16-bit values, and adds or subtract s the multiplication result from one 40-bit value, and outputs a 40-bit value. the mac is provided with a shifter (msft: mac shifter) at the stage preceding the input stage. this shifter can arithmetically shift the 40-bit value to be added to or subtracted from the multiplicat ion result 1 or 16 bits to the right . 2.2.3 arithmetic logic unit (alu) this unit inputs one or two 40-bit values, executes an arit hmetic or logical operation, and outputs a 40-bit value. 2.2.4 barrel shifter (bsft: barrel shifter) the barrel shifter inputs a 40-bit value, shifts it to the le ft or right by any number of bi ts, and outputs a 40-bit value. the data may be arithmetically shifted to the right shifted to the right, in which case the dat a is sign-extended, or logically shifted to the right, in whic h case 0 is inserted from the msb.
data sheet u14867ej5v0ds 17 pd77115, 77115a 2.3 data memory unit the data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 data memory the dsp have two banks of data memory (x data memory and y data memory). a 64-word peripheral area is assigned in the data memory space. the pd77115 has 16k words 2 banks data ram. 2.3.2 data addressing unit an independent data addressing unit is provided for each of the x data memory and y data memory spaces. each data addressing unit has four data poi nters (dpn), four index registers (dnn), one modulo register (dmx or dmy), and an address alu. 2.4 peripheral unit a serial interface, host interface, general-purpose i/o port, and wait cycle register are prov ided. all these internal peripherals are mapped to the x data memory and y data memory spaces, and are accessed from program as memory-mapped i/os. 2.4.1 audio serial interface (asio) one serial interface is provided. this serial inte rface has two mode which are the audio serial and the standard serial. the standard serial is compatible other pd77111 family dsp. the audio serial interfaces have the following features: mode : master mode or slave mode master mode : mclk (input), bclk (output), lrclk (output), support 256 fs, 384 fs and 512 fs slave mode : mclk (unused), bclk (input), lrclk (input) frame format : 32 or 64 bits audio format (lrclk format), msb first input/output. handshake : handshaking with the external devices is im plemented with a dedicated frame signal (lrclk). handshaking with the internal units, po lling, wait, or interrupt are used. the standard serial interfaces have the following features: serial clock : supplied from external source to each interfac e. the same clock is used for input and output on the interface. frame length : 8 or 16 bits, and msb or lsb first selectable for each input or output handshake : handshaking with external devices is implemented with a dedicated status signal. with the internal units, polling, wait, or interrupt are used. 2.4.2 host interface (hio) this is an 16-bit parallel port that input s data from or outputs data to an external host cpu or dma controller. in the dsp, a 16-bit register is mapped to memory for input data, output data, and status. h andshaking with an external device is implemented by using a dedicat ed status signal or a dedica ted status register. handshaking with internal units is achieved by means of polling, wait, or interrupts.
data sheet u14867ej5v0ds 18 pd77115, 77115a 2.4.3 general-purpose i/o port (pio) this is a 8-bit i/o port that can be set in the input or output mode in 1-bit units. 2.4.4 sd card interface (sdcif) this interface is for access sd card. it supports the dma tr ansfer for input data to internal data ram. the sd card is accessed by using a dedica ted routine of system rom. 2.4.5 timer this is 16-bit timer unit. the count source can be selected fr om system clock, sd card cl ock, serial clock and int4 input. timer unit generates interrupt for interface internal units. 3. reset function when a low level of a specified width is input to the reset pin, the device is initialized. 3.1 hardware reset if the reset pin is asserted active (low level) for a specified period, the internal circuitry of the dsp is initialized. if the reset pin is then deasserted inactive (high level), boot processing of the instruction ram is performed according to the status of the port pins (p0 and p1 ). after boot processing, processing is executed starting fr om the instruction at address 0x200 of instruction memory (reset entry). no power-on reset function is available. 3.2 initializing pll initializing the pll starts dur ing boot up program at reset. the pins (pll0 to pll3) that specif y the pll multiple rate must be kept stable for the dur ation of 3 clocks before and for the dur ation of 50 clocks after reset has been cleared (the clock is input from clkin). it takes the pll 100 s to be locked. until the pll is lacked, the dsp internal is operated by the clkin clock. to use the pll clock as an internal operating clock, set the clock control register (i nternal peripheral) by user program. 4. functions of boot-up rom to rewrite the contents of the instruction memory on power application or from program, boot up the instruction ram by using the internal boot-up rom. the pd77115 has a function to verify the content s of the internal instruction ram. 4.1 boot at reset after hardware reset has been cleared, the boot program first reads the gener al-purpose i/o ports p0 and p1 and, depending on their bit pattern, determines the boot mode (host boot or non boot). after boot processing, processing is executed starting from the instru ction at address 0x200 (reset entry) of the instruction memory. the pins (p0 and p1) that s pecify the boot mode must be k ept stable for the duration of 3 clocks before and for the duration of 12 clocks after reset has been cl eared (the clock is input from clkin).
data sheet u14867ej5v0ds 19 pd77115, 77115a p1 p0 boot mode 0 0 does not execute boot but branches to address 0x200 note . 0 1 executes host byte boot and then branches to address 0x200. 1 0 setting prohibited 1 1 executes host word boot and then branches to address 0x200. note this setting is used when the dsp must be reset to recover from the standby mode after reset boot has been executed once. a boot parameter and instructi on code are obtained via the host interface, and transferred to the instruction ram. the data transfer support byte mode and word mode. 4.2 reboot by calling the reboot entry address from the program, the contents of the instruction ram can be rewritten. an instruction code is obtained via the host interface and transferred to the instru ction ram. the data transfer support byte mode and word mode. the entry address is 0x6. host r eboot is executed by calling this addre ss after setting the following parameter: r7l : number of instruction steps for rebooting dp3 : first address of instruction memory to be loaded 4.3 signature operation the pd77115 has a signature operation functi on so that the content s of the internal instruction ram can be verified. the signature operation performs a specific arithmetic operation on the data in the instruction ram booted up, and returns the result to a register. perform the si gnature operation in advance on t he device when it is operating normally, and repeat the signature operation later to check whether the data in ram is correct by comparing the operation result with the previous result. if the results are identical , there is no problem. the entry address is 0x9. execute t he operation by calling this address afte r setting the following parameter. the operation result is stored in register r7. r7l: number of inst ruction steps for operation dp3: first address of instruction memory for operation
data sheet u14867ej5v0ds 20 pd77115, 77115a 5. standby modes two standby modes are available. by executing the corresponding instruct ion, each mode is set and the power consumption can be reduced. 5.1 halt mode to set this mode, execute the halt instruction. in this mode, functi ons other than clock circuit and pll are stopped to reduce the cu rrent consumption. to release the halt mode, use an inte rrupt or hardware reset. when releas ing the halt mode using an interrupt, the contents of the internal registers and memory are retained. it takes several 10 system clocks to release the halt mode when the halt mode is released using an interrupt. in the halt mode, the clock circuit of the pd77115 supplies the following clock as the internal system clock. the clock output from the clkout pin is also as follows. the clock output from the clko ut pin, however, has a high-level width t hat is equivalent to 1 cycle of the normal operation (i.e., the duty factor is not 50%). pd77115: 1/l of internal system clock (l = in teger from 1 to 16, specified by register) 5.2 stop mode to set the stop mode, execute the st op instruction. in the stop mode, all the functions, including the clock circuit and pll, can be stopped and the power consumption is minimized with only leakage current flowing. to release the stop mode, use hardware reset or wakeup pin. when releasing the stop mode by usi ng the wakeup pin, the c ontents of the internal registers and memory are retained, but it takes several 100 s to release the mode.
data sheet u14867ej5v0ds 21 pd77115, 77115a 6. memory map a harvard architecture, in which the instruction memory space and data memory space are separated is employed. 6.1 instruction memory 6.1.1 instruction memory map 0xffff 0x0240 0x023f 0x0200 0x01ff 0x0000 system instruction ram (8k words) vector area (64 words) boot-up rom (512 words) 0x1000 0x0fff instruction ram (3.5k words) system 0x8000 0x7fff 0xa000 0x9fff caution programs and da ta cannot be placed at addresses r eserved for the system, nor can these addresses be accessed. if these addresses are accessed , the normal operation of the device cannot be guaranteed.
data sheet u14867ej5v0ds 22 pd77115, 77115a 6.1.2 interrupt vector table addresses 0x200 to 0x23f of the instru ction memory are entry points (vectors ) of interrupts. four instruction addresses are assigned to each interrupt source. vector interrupt source 0x200 reset 0x204 0x208 0x20c reserved 0x210 int1 0x214 int2 0x218 int3 0x21c int4 0x220 si input 0x224 so output 0x228 sddat input / pbu 0x22c sddat output 0x230 hi input 0x234 ho output 0x238 sdcr input 0x23c timer cautions 1. although reset is not an interrupt, it is handled like an interrupt as an entry to a vector. 2. it is recommended that unused interrupt source vectors be used to branch an error processing routine.
data sheet u14867ej5v0ds 23 pd77115, 77115a 6.2 data memory 6.2.1 data memory map 0xffff 0x0000 data ram (8k words) 0x6000 0x5fff peripheral (64 words) system data ram (4k words) system system 0x0fff 0x3800 0x383f 0x3840 0x3fff 0x4000 system data ram (4k words) 0x2fff 0x2000 0x1000 0x3000 0x37ff 0x1fff caution programs and da ta cannot be placed at addresses r eserved for the system, nor can these addresses be accessed. if these addresses are accessed , the normal operation of the device cannot be guaranteed.
data sheet u14867ej5v0ds 24 pd77115, 77115a 6.2.2 internal peripherals the internal peripherals are mapped to the internal data memory space. x/y memory address register name function peripheral name 0x3800 sdt/asdt serial data register 0x3801 sst serial status register 0x3802 asst audio serial status register asio 0x3803 reserved area caution do not access this area. ? 0x3804 pdt port data register 0x3805 pcd port command register pio 0x3806 hdt host data register 0x3807 hst host status register hio 0x3808 to 0x380f reserved area caution do not access this area. ? 0x3810 sddr sd card data register 0x3811 sdcmd_idx sd card command register index 0x3812 sdcmd_agh sd card command register argument high 0x3813 sdcmd_agl sd card command register argument low 0x3814 sdctl sd card control register 0x3815 sdrpr sd card response register 0x3816 sdsbr sd card crc status busy register sdcif 0x3817 to 0x381f reserved area caution do not access this area. ? 0x3820 tir timer initialize value register 0x3821 tcr timer count register 0x3822 tcsr timer control / status register 0x3823 tenr timer count enable register timer 0x3824 to 0x382d reserved area caution do not access this area. ? 0x382e clkcntl clock control register pll 0x382f reserved area caution do not access this area. ? 0x3830 psar dma start address register 0x3831 psr dma size register 0x3832 prr dma pointer register 0x3833 pcr dma control register sdcif 0x3834 to 0x383f reserved area caution do not access this area. ? cautions 1. the register names lis ted in this table are not reserved words of the assembler or the c language. therefore, when using these names in assembler or c, the user must define them. 2. the same register is accessed, as long as the address is the same, regardless of whether the x memory space or y memory space is accessed. 3. even different registers cannot be accessed at the same time from both the x and y memory spaces.
data sheet u14867ej5v0ds 25 pd77115, 77115a 7. instructions 7.1 outline of instructions an instruction consists of 32 bits. almost all the inst ructions, except some such as branch instructions, are executed with one system cl ock. the maximum instruction cycle of the pd77115 is 13.3 ns. the following nine types of instructions are available: (1) trinomial opera tion instructions these instructions specif y an operation by the mac. as the oper ands, three general-purpose registers can be specified. (2) binomial operation instructions these instructions specif y an operation by the mac, alu, or bs ft. as the operands, two general-purpose registers can be specified. an imm ediate value can be specified for some of these instructions, instead of a general-purpose register, for one input. (3) uninominal operation instructions these instructions specif y an operation by the alu. as the operands, one general-purpos e register can be specified. (4) load/store instructions these instructions transfer 16-bit values between me mory and a general-purpose regi ster. any general-purpose register can be specified as the transfer source or destination. (5) register-to-register transfer instructions these instructions transfer data from one general-purpose register to another. (6) immediate value setting instructions these instructions write an immedi ate value to a general-purpose regist er and the registers of the address operation unit. (7) branch instructions these instruction specify branc hing of program execution. (8) hardware loop instructions these instruction spec ify repetitive executi on of an instruction. (9) control instructions these instructions are us ed to control the program.
data sheet u14867ej5v0ds 26 pd77115, 77115a 7.2 instruction set and operation an operation is written in the operation field for each instruction in accordance with the oper ation representation format of that instruction. if two or more parameters can be written, select one of them. (a) representation formats and selectable registers the following table shows t he representation formats and selectable registers. representation format selectable register r0, r0?, r0? r0 to r7 ri, ri? r0l to r7l rh, rh? r0h to r7h re r0e to r7e reh r0eh to r7eh dp dp0 to dp7 dn dn0 to dn7 dm dmx, dmy dpx dp0 to dp3 dpy dp4 to dp7 dpx_mod dpn, dpn++, dpn ? ? , dpn##, dpn%%, !dpn## (n = 0 to 3) dpy_mod dpn, dpn++, dpn ? ? , dpn##, dpn%%, !dpn## (n = 4 to 7) dp_imm dpn##imm (n = 0 to 7) *xxx contents of memory with address xxx if the contents of the dp0 register are 1000, *dp0 indicates the contents of address 1000 of the memory.
data sheet u14867ej5v0ds 27 pd77115, 77115a (b) modifying data pointer the data pointer is modified after t he memory has been accessed. the resu lt of modification becomes valid starting from the instruction t hat immediately follows. the data pointer cannot be modified. example operation dpn nothing is done (value of dpn is not changed.) dpn++ dpn dpn + 1 dpn ? ? dpn dpn ? 1 dpn## dpn dpn + dnn (adds value of corresponding dn0 to dn7 to dp0 to dp7.) example: dp0 dp0 + dn0 (n = 0 to 3) dpn = ((dp l + dnn) mod (dmx + 1)) + dp h dpn%% (n = 4 to 7) dpn = ((dp l + dnn) mod (dmy + 1)) + dp h !dpn## reverses bits of dpn and then accesses memory. after memory access, dpn dpn + dnn dpn##imm dpn dpn + imm (c) instructions that can be simultaneously written instructions that can be simultaneous ly written are indicated by o. (d) status of overflow flag (ov) the status of the overflow flag is indicated by the following symbol: ? : not affected : set to 1 when overflow occurs caution if an overflow does not o ccur as a result of an operation, th e overflow flag is not reset but retains the status before the operation.
data sheet u14867ej5v0ds 28 pd77115, 77115a instruction set instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate value bran- ch loop cont- rol ov multiply add ro = ro + rh * rh? ro ro + rh * rh? multiply sub ro = ro ? rh * rh? ro ro ? rh * rh? sign unsign multiply add ro = ro + rh * rl (rl is in positive integer format.) ro ro + rh * rl unsign unsign multiply add ro = ro + rl * rl? (rl and rl? are in positive integer format.) ro ro + rl * rl? 1-bit shift multiply add ro = (ro>>1) + rh * rh? ro ro 2 + rh * rh? trinomial operation 16-bit shift multiply add ro = (ro>>16) + rh * rh? ro ro 2 16 + rh * rh? ? multiply ro = rh * rh? ro rh * rh? ? add ro? = ro + ro? ro? ro + ro? immediate add ro? = ro + imm ro? ro + imm (where imm 1) sub ro? = ro ? ro? ro? ro ? ro? immediate sub ro? = ro ? imm ro? ro ? imm (where imm 1) arithmetic right shift ro? = ro sra rl ro? ro >> rl ? immediate arithmetic right shift ro? = ro sra imm ro? ro >> imm ? logical right shift ro? = ro srl rl ro? ro >> rl ? immediate logical right shift ro? = ro srl imm ro? ro >> imm ? logical left shift ro? = ro sll rl ro? ro << rl ? immediate logical left shift ro? = ro sll imm ro? ro << imm ? and ro? = ro & ro? ro? ro & ro? ? immediate and ro? = ro & imm ro? ro & imm ? or ro? = ro ? ro? ro? ro ? ro? ? immediate or ro? = ro ? imm ro? ro ? imm ? exclusive or ro? = ro ro? ro? ro ro? ? binomial operation immediate exclusive or ro? = ro imm ro? ro imm ?
data sheet u14867ej5v0ds 29 pd77115, 77115a instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate value bran- ch loop cont- rol ov binomial operation less than ro? = lt (ro, ro?) if (ro < ro ? ) {ro? 0x0000000001} else {ro? 0x0000000000} ? clear clr (ro) ro 0x0000000000 ? increment ro? = ro + 1 ro? ro + 1 decrement ro? = ro ? 1 ro? ro ? 1 absolute value ro? = abs (ro) if (ro < 0) {ro? ? ro} else {ro? ro} 1?s complement ro? = ~ ro ro? ~ ro ? 2?s complement ro? = ? ro ro? ? ro clip ro? = clip (ro) if ( ro > 0x007fffffff) {ro? 0x007fffffff} elseif {ro < 0xff80000000} {ro? 0xff80000000} else {ro? ro} ? round ro? = round (ro) if (ro > 0x007fff0000) {ro ? 0x007fff0000} elseif {ro < 0xff80000000} {ro ? 0xff80000000} else {ro ? (ro + 0x8000) & 0xffffff0000} ? exponent ro? = exp (ro) ro? log 2 ( 1 ro ) ? substitution ro? = ro ro? ro ? accumulated addition ro? + = ro ro? ro? + ro accumulated subtraction ro? ? = ro ro? ro? ? ro uninom- inal operation division ro? / = ro if (sign (ro ? ) == sign (ro)) {ro ? (ro ? ? ro) << 1} else {ro ? (ro ? + ro)<<1} if (sign (ro ? )==0) {ro ? ro ? + 1}
data sheet u14867ej5v0ds 30 pd77115, 77115a instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate value bran- ch loop cont- rol ov ro = *dpx_mod ro? =*dpy_mod ro *dpx, ro ? *dpy ro = *dpx_mod *dpy_mod = rh ro *dpx, *dpy rh *dpx_mod = rh ro = *dpy_mod *dpx rh, ro *dpy parallel load/store notes 1, 2 *dpx_mod = rh *dpy_mod = rh? *dpx rh, *dpy rh? ? dest = *dpx_mod dest = *dpy_mod dest *dpx, dest *dpy dest = *dpx_mod *dpy_mod = source dest *dpx, *dpy source *dpx_mod = source dest = *dpy_mod *dpx source, dest *dpy partial load/ store notes 1, 2, 3 *dpx_mod = source *dpy_mod = source? *dpx source, *dpy source? ? dest = *addr dest *addr direct addressing load/store note 4 *addr = source *addr source ? dest = *dp_imm dest *dp load/ store immediate value index load/store note 5 *dp_imm = source *dp source ? dest = rl dest rl register- to-register transfer register-to- register transfer note 6 rl = source rl source ? rl = imm (where imm = 0 to 0xffff) rl imm dp = imm (where imm = 0 to 0xffff) dp imm dn = imm (where imm = 0 to 0xffff) dn imm immediate value setting immediate value setting dm = imm (where imm = 1 to 0xffff) dm imm ? notes 1. of the two mnemonics, either one of them or both can be written. 2. after transfer, modification specified by mod is performed. 3. select any of dest, dest? = {ro, reh, re, rh, rl}, source, source? = {re, rh, rl}. 4. select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, 0: x-0xfff 0: y-0xffff : x (x memory) : y (y memory) addr = . 5. select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 6. select any register other than general -purpose registers as dest and source.
data sheet u14867ej5v0ds 31 pd77115, 77115a instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate value bran- ch loop cont- rol ov jump jmp imm pc imm ? register indirect jump jmp dp pc dp ? subroutine call call imm sp sp + 1 stk pc + 1 pc imm ? register indirect subroutine call call dp sp sp + 1 stk pc + 1 pc dp ? return ret pc stk sp sp ? 1 ? branch interrupt return reti pc stk stk sp ? 1 recovery of interrupt enable flag ? repeat rep count start rc count rf 0 during repeat pc pc rc rc ? 1 end pc pc + 1 rf 1 ? loop loop count (instruction of two or more lines) start rc count rf 0 during repeat pc pc rc rc ? 1 end pc pc + 1 rf 1 ? hard- ware loop loop pop lpop lc lsr3 le lsr2 ls lsr1 lsp lsp ? 1 ? no operation nop pc pc + 1 ? halt halt cpu stops. ? stop stop cpu, pll, and osc stop ? condition if (ro cond) condition test ? control forget interrupt fint discard interrupt request ?
data sheet u14867ej5v0ds 32 pd77115, 77115a 8. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol condition rating unit iv dd for dsp core ? 0.5 to +3.6 v supply voltage ev dd for i/o pins ? 0.5 to +4.6 v input voltage v i ? 0.5 to +4.1 v output voltage v o v i < ev dd + 0.5 v ? 0.5 to +4.1 v storage temperature t stg ? 65 to +150 c operating ambient temperature t a ? 40 to +85 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated valu es at which the product is on the verge of suffering physical damage, and theref ore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions parameter symbol condition min. typ. max. unit iv dd for dsp core 2.0 2.7 v operating voltage ev dd for i/o pins 2.7 3.6 v input voltage v i 0 ev dd v capacitance (t a = +25 c, iv dd = 0 v, ev dd = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i 10 pf output capacitance c o 10 pf i/o capacitance c io f = 1 mhz, pins other than those tested: 0 v 10 pf
data sheet u14867ej5v0ds 33 pd77115, 77115a dc characteristics (unless otherwise specified, t a = ? 40 to + 85 c, with iv dd and ev dd within recommended operating condition range) parameter symbol condition min. typ. max. unit v ihn pins other than below 0.7 ev dd ev dd v v ihs reset, int1 to int4, sck, sien, soen 0.8 ev dd ev dd v high-level input voltage v ihc clkin 0.5 ev dd +0.25 ev dd v v il pins other than below 0 0.2 ev dd v low-level input voltage v ic clkin 0 0.5 ev dd ?0.25 v i oh = ? 2.0 ma 0.7 ev dd v high-level output voltage v oh i oh = ? 100 a 0.8 ev dd v low-level output voltage v ol i ol = 2.0 ma 0.2 ev dd v high-level input leakage current i lh other than tdi, tms, and trst v i = ev dd 0 10 a low-level input leakage current i ll other than tdi, tms, and trst v i = 0 v ? 10 0 a pull-up pin current i pui tdi, tms, 0 v v i ev dd ? 250 0 a pull-down pin current i pdi trst, 0 v v i ev dd 0 250 a i dd note during operating, 30 ns, iv dd = 2.7 v tbd 75 ma i ddh in halt mode, t cc = 30 ns, divided by eight, iv dd = 2.7 v tbd 10 ma internal supply current [v ihn = v ihs = ev dd , v il = 0 v, no load] i dds in stop mode, 0 c < t a < 60 c 100 a note the typ. values are when an or dinary program is executed. the max. values are when a specia l program that brings about frequent switching inside the device is executed.
data sheet u14867ej5v0ds 34 pd77115, 77115a common test criteria of switching characteristics 0.8 ev dd 0.5 ev dd 0.2 ev dd 0.8 ev dd 0.5 ev dd 0.2 ev dd test points reset, int1 to int4, sck, sien, soen 0.7 ev dd 0.5 ev dd 0.2 ev dd 0.7 ev dd 0.5 ev dd 0.2 ev dd test points input (other than above) 0.5 ev dd + 0.25 0.5 ev dd 0.5 ev dd ? 0.25 0.5 ev dd + 0.25 0.5 ev dd 0.5 ev dd ? 0.25 test points clkin 0.5 ev dd 0.5 ev dd test points output
data sheet u14867ej5v0ds 35 pd77115, 77115a ac characteristics (t a = ? 40 to + 85 c, with iv dd and ev dd within recommended ope rating condition range) clock timing requirements parameter symbol condition min. typ. max. unit 25 ns iv dd = 2.0 to 2.7 v 15 m 50 m ns clkin cycle time note 1 t ccx pll lock range note 2 iv dd = 2.3 to 2.7 v 10 m 50 m ns clkin high-level width t wcxh 12.5 ns clkin low-level width t wcxl 12.5 ns clkin rise/fall time t rfcx 5 ns iv dd = 2.0 to 2.7 v 20 ns internal clock cycle time requirements note 3 t cc (r) iv dd = 2.3 to 2.7 v 13.3 ns notes 1. m: multiple 2. this is the range in which the pll is locked (stably oscillates). input t ccx within this range. 3. input t ccx so that the value of (t ccx m n) satisfies this condition. m: multiple, n: division ratio switching characteristics parameter symbol condition min. typ. max. unit internal clock cycle note t cc external clock operation t ccx ns pll clock operation (t ccx m) n ns in halt mode (t ccx m) n l ns clkout cycle time t cco t cc ns n = 1, or even number t cc 2 ? 3 ns during normal operation n = odd number (other than 1) t cc n ? 3 ns clkout width t wco in halt mode t cc n ? 3 ns clkout rise/fall time t rfco 5 ns iv dd = 2.0 to 2.7 v 20 ns clkout delay time t dco iv dd = 2.3 to 2.7 v 15 ns note m: multiple, n: division ratio, l: halt division ratio
data sheet u14867ej5v0ds 36 pd77115, 77115a clock i/o timing internal clock clkin clkout t ccx t cc, t cc(r) t wcxh t wcxl t rfcx t rfcx t cco t dco t wco t wco t rfco t rfco
data sheet u14867ej5v0ds 37 pd77115, 77115a reset, interrupt timing requirements parameter symbol condition min. typ. max. unit reset low-level width t w (rl) 6 t cc note ns wakeup low-level width t w (wakeupl) 6 t cc s int1 to int4 low-level width t w (intl) 3 t cc note ns int1 to int4 recovery time t rec (int) 3 t cc ns note note that t cc is i (i = integer of 1 to 16) times t hat during normal operati on in the halt mode. reset timing reset t w(rl) wakeup timing wakeup t w (wakeupl) interrupt timing int1 to int4 t w(intl) t rec(int)
data sheet u14867ej5v0ds 38 pd77115, 77115a serial interface (audio serial mode) timing requirements parameter symbol condition min. typ. max. unit mclk cycle time t cmc master mode 40 ns mclk high-/low-level width t wmc master mode 0.4 t cmc ns mclk rise/fall time t rfmc master mode note ns bclk cycle time t cbc slave mode 300 ns bclk high-/low-level width t wbc slave mode 120 ns bclk rise/fall time t rfbc slave mode 20 ns lrclk setup time t su(bc-lr) slave mode 50 ns si setup time t susi 50 ns si hold time t hsi 50 ns note 5 or maximum value of 0.1 t cmc switching characteristics parameter symbol condition min. typ. max. unit bclk cycle time t cbc master mode, 64-bit mode 1/64 fs ns master mode, 32-bit mode 1/32 fs ns bclk high-/low-level width t wbc master mode 0.4 t cbc ns bclk rise/fall time t rfbc master mode 20 ns lrclk delay time t d(bc-lr) master mode ? 40 + 40 ns so output delay time t dso ? 40 + 40 ns
data sheet u14867ej5v0ds 39 pd77115, 77115a audio serial clock timing mclk t cmc t wmc t wmc t rfmc t rfmc audio serial master mode timing bclk (output) t rfbc lrclk (output) t d(bc-lr) t wbc t wbc t cbc t d(bc-lr) t rfbc so t dso si t hsi t susi audio serial slave mode timing bclk (input) t rfbc lrclk (input) t su(bc-lr) t wbc t wbc t cbc t rfbc so t dso si t hsi t susi t su(bc-lr)
data sheet u14867ej5v0ds 40 pd77115, 77115a serial interface (standard serial mode) timing requirements parameter symbol condition min. typ. max. unit sck cycle time t csc 60 and 2t cc ns sck high-/low-level width t wsc 25 ns sck rise/fall time t rfsc 20 ns iv dd = 2.0 to 2.7 v 10 ns soen setup time t susoe iv dd = 2.3 to 2.7 v 5 ns iv dd = 2.0 to 2.7 v 15 ns soen hold time t hsoe iv dd = 2.3 to 2.7 v 10 ns iv dd = 2.0 to 2.7 v 10 ns sien setup time t susie iv dd = 2.3 to 2.7 v 5 ns iv dd = 2.0 to 2.7 v 15 ns sien hold time t hsie iv dd = 2.3 to 2.7 v 10 ns iv dd = 2.0 to 2.7 v 10 ns si setup time t susi iv dd = 2.3 to 2.7 v 5 ns iv dd = 2.0 to 2.7 v 15 ns si hold time t hsi iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 2.0 to 2.7 v 30 ns so output delay time t dso iv dd = 2.3 to 2.7 v 25 ns so hold time t hso 0 ns
data sheet u14867ej5v0ds 41 pd77115, 77115a serial output timing 1 sck t rfsc soen so 1st last t hso t dso t dso t hsoe t susoe t susoe t hsoe t wsc t wsc t csc t rfsc hi-z serial output timing 2 (during successive output) sck t rfsc soen so 1st last t dso t hsoe t susoe t wsc t wsc t csc t rfsc last t hso
data sheet u14867ej5v0ds 42 pd77115, 77115a serial input timing 1 sck sien si t csc t wsc t wsc t susie t hsie t susie t hsie t susi t hsi 1st 2nd t rfsc t rfsc 3rd serial input timing 2 (during successive input) sck sien si t csc t wsc t wsc t susie t hsie t susi t hsi 1st 3rd t rfsc t rfsc last last?1 2nd
data sheet u14867ej5v0ds 43 pd77115, 77115a caution if noise is superimposed on the serial clock, the serial interface may be deadlocked. bear in mind the following points when designing your system: ? reinforce the wiring for power supply and gr ound (if noise is superimposed on the power and ground lines, it has the same effect as if noi se were superimposed on the serial clock). shorten the wiring between the device' s sck pin, and clock supply source. do not cross the signal lines of the serial clo ck with any other signal lines. do not route the serial clock line in the vicini ty of a line through which a high alternating current flows. supply the clock to the sck pin of the device from the clock s ource on a one-to-one basis. do not supply clock to several d evices from one clock source. exercise care that the serial cl ock does not overshoot or undershoot . in particular, make sure that the rising and falling of th e serial clock waveform are clear. make sure that the serial clock rises and falls linearly. the serial clock must not bound. noise must not be superimposed on the serial clock. the serial clock must not rise or fall step-wise.
data sheet u14867ej5v0ds 44 pd77115, 77115a host interface timing requirements parameter symbol condition min. typ. max. unit iv dd = 2.0 to 2.7 v 15 ns hrd delay time t dhr iv dd = 2.3 to 2.7 v 5 ns hrd width t whr 40 ns hcs, ha0, ha1, read hold time t hhcar 0 ns hcs, ha0, ha1 write hold time t hhcaw 0 ns hrd, hwr recovery time t rechs 3t cc ns iv dd = 2.0 to 2.7 v 15 ns hwr delay time t dhw iv dd = 2.3 to 2.7 v 10 ns hwr width t whw 40 ns hwr hold time t hhdw 0 ns iv dd = 2.0 to 2.7 v 15 ns hwr setup time t suhdw iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 2.0 to 2.7 v 30 ns hre, hwe output delay time t dhe iv dd = 2.3 to 2.7 v 25 ns iv dd = 2.0 to 2.7 v 30 ns hre, hwe hold time t hhe iv dd = 2.3 to 2.7 v 25 ns iv dd = 2.0 to 2.7 v 30 ns hrd valid time t vhdr iv dd = 2.3 to 2.7 v 25 ns hrd hold time t hhdr 0 ns
data sheet u14867ej5v0ds 45 pd77115, 77115a host read interface timing clkin hrd t dhe t hhdr t hhcar t rechs t vhdr t whr t dhr t hhe hcs, ha0, ha1 hd0 to hd15 hre hi-z hi-z host write interface timing clkin hwr t dhe t hhdw t hhcaw t rechs t whw t dhw t hhe hcs, ha0, ha1 hd0 to hd15 hwe t suhdw
data sheet u14867ej5v0ds 46 pd77115, 77115a general-purpose i/o port timing requirements parameter symbol condition min. typ. max. unit port input setup time t supi 0 ns iv dd = 2.0 to 2.7 v 15 ns port input hold time t hpi iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 2.0 to 2.7 v 30 ns port output delay time t dpo iv dd = 2.3 to 2.7 v 25 ns general-purpose i/o port timing clkin p0 to p7 (output) t dpo t hpi t supi p0 to p7 (input)
data sheet u14867ej5v0ds 47 pd77115, 77115a sd card interface timing requirements parameter symbol condition min. typ. max. unit sdcr input setup time t susdcr input response 5 ns sdcr input hold time t hsdcr input response 0 ns sddat input setup time t susdd input data 5 ns sddat input hold time t hsdd input data 0 ns switching characteristics parameter symbol condition min. typ. max. unit sdclk cycle time t csdc 40 ns sdclk high- level width t wsdch 10 ns sdclk low-level width t wsdcl 10 ns sdclk rise/fall time t rfsdc 10 ns sdcr output delay time t dsdcr output command 10 ns sdcr output valid time t vsdcr output command 0 ns sddat output delay time t dsdd output data 10 ns sddat output valid time t vsdd output data 0 ns
data sheet u14867ej5v0ds 48 pd77115, 77115a sdcr timing sdclk sdcr (output) t dsdcr t hsdcr t susdcr sdcr (input) t vsdcr t csdc t wsdcl t wsdch t rfsdc t rfsdc sddat timing sdclk sddat (output) t dsdd t hsdd t susdd sddat (input) t vsdd t csdc t wsdcl t wsdch t rfsdc t rfsdc
data sheet u14867ej5v0ds 49 pd77115, 77115a debugging interface (jtag) timing requirements parameter symbol condition min. typ. max. unit tck cycle time t ctck 120 ns tck high-/low-level width t wtck 50 ns tck rise/fall time t rftck 20 ns iv dd = 2.0 to 2.7 v 25 ns tms, tdi setup time t sudi iv dd = 2.3 to 2.7 v 20 ns iv dd = 2.0 to 2.7 v 25 ns tms, tdi hold time t hdi iv dd = 2.3 to 2.7 v 20 ns iv dd = 2.0 to 2.7 v 25 ns input pin setup time t sujin iv dd = 2.3 to 2.7 v 20 ns iv dd = 2.0 to 2.7 v 25 ns input pin hold time t hjin iv dd = 2.3 to 2.7 v 20 ns trst setup time t sutrst 100 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 2.0 to 2.7 v 25 ns tdo output delay time t ddo iv dd = 2.3 to 2.7 v 20 ns iv dd = 2.0 to 2.7 v 25 ns output pin output delay time t djout iv dd = 2.3 to 2.7 v 20 ns
data sheet u14867ej5v0ds 50 pd77115, 77115a debugging interface timing t ctck t wtck t sutrst t sudi t hdi t ddo t sujin t hjin valid valid t djout t wtck t rftck t rftck valid valid tck trst tms, tdi tdo capture state update state remark for details of jtag, refer to ieee1149.1 .
data sheet u14867ej5v0ds 51 pd77115, 77115a 9. packages item dimensions d e w a a1 a2 e 9.00 0.10 9.00 0.10 0.80 0.20 0.35 0.06 1.28 0.10 0.93 (unit:mm) 0.08 0.10 0.20 1.30 1.30 p80f1-80-cn6 0.50 +0.05 ?0.10 x y y1 zd ze b s wb s wa zd ze index mark b a 1 a b c d e f g h j 2 3 4 5 6 7 8 9 d e s e x ba b m ? s a a2 a1 y1 s s y 80-pin plastic fbga (9x9)
data sheet u14867ej5v0ds 52 pd77115, 77115a 60 41 40 21 61 80 120 80-pin plastic tqfp (fine pitch) (12x12) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 14.0 0.2 12.0 0.2 1.25 14.0 0.2 c 12.0 0.2 0.10 i j h 0.22 0.05 0.5 (t.p.) k 1.0 0.2 f 1.25 m 0.145 0.05 1.0 0.05 p q n 0.10 0.1 0.05 l 0.5 0.2 s80gk-50-9eu-1 s 1.2 max. r3 + 7 ? 3 m s s n j detail of lead end c d a b r k m l p i s q g f h
data sheet u14867ej5v0ds 53 pd77115, 77115a 10. recommended soldering conditions it is recommended to solder this product under the following conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) surface-mount type ? pd77115gk-9eu: 80-pin plastic tqfp (fine-pitch) (12 12) soldering process solder ing conditions symbol infrared ray reflow package peak temperature: 235c, time: 30 seconds max (210c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 to 72 hours at 125c)) ir35-103-2 vps package peak temperature: 215c, time: 40 seconds max (200c min), number of times: 2 max, number of days: 3 note (after that, prebaking isnecessary for 10 to 72 hours at 125c) vp15-103-2 partial heating method pin temperature: 300c max, time: 3 seconds max ( per side of device) ? ? pd77115f1-cn6: 80-pin plastic fbga (9 9) ? pd77115af1-xxx-cn6: 80-pin plastic fbga (9 9) soldering process solder ing conditions symbol infrared ray reflow package peak temperature: 235c, time: 30 seconds max (210c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 to 72 hours at 125c)) ir35-103-2 vps package peak temperature: 215c, time: 40 seconds max (200c min), number of times: 2 max, number of days: 3 note (after that, prebaking isnecessary for 10 to 72 hours at 125c) vp15-103-2 note number of days in storage after the dry pack has been opened. the storage conditi ons are at 25c, 65% rh max. caution apply wave soldering only to th e pins and be careful not to bri ng solder into direct contact with the package.
data sheet u14867ej5v0ds 54 pd77115, 77115a regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
data sheet u14867ej5v0ds 55 pd77115, 77115a 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd77115, 77115a these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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